1. Field of the Invention
The present invention relates to the field of semiconductor processing, and more specifically, to polishing methods and polishing pads for planarizing semiconductor materials in the fabrication of semiconductor devices.
2. Background Information
Semiconductor devices manufactured today generally rely upon an elaborate system of semiconductor device layers, patterns, and interconnects. The techniques for forming such various device layers, patterns, and interconnects are extremely sophisticated and are well understood by practitioners in the art. During fabrication, however, these varying device layers, patterns, and interconnects often create non-planar wafer topographies. Such non-planar wafer topographies cause difficulties when forming subsequent device layers, insulating layers, levels of interconnects, etc.
Some problems associated with non-planar topographies, for example, are the interference and scattering of radiation by the non-planar topography when performing photolithographic process steps. This makes it particularly difficult to print patterns with high resolution. Another problem with non-planar topographies is in depositing metal layers or lines. Uneven topographies, or step-heights as they are often called, may cause thinning of the metal line/layer at points where the topography transitions from a high point to a low point, and vice versa. Such thinning of the metal layers may cause open circuits to be formed in the device or may cause the device to suffer reliability problems.
To combat these problems, various techniques have been developed in an attempt to planarize the topography of the wafer surface prior to performing additional processing steps. One approach employs abrasive polishing, for example chemical mechanical polishing (CMP), to remove the high points along the upper surface. According to this method, the wafer is placed on a table and is polished with a pad that has been coated with an abrasive material (i.e. slurry). Both the wafer and the table are rotated relative to each other to remove the high portions of the wafer topography. This abrasive polishing process continues until the upper surface of the wafer is largely planarized.
One problem with polishing to planarize the topography is that the polishing rates can become unstable and/or uneven across the surface of the wafer. For example, the profile of the topography in certain areas of the wafer may affect the polishing rate in that area. FIG. 1 illustrates a simple example of the polishing rate profile of a wafer 100. As is illustrated in FIG. 1, the polishing rate at the edges 110 of wafer 100 is slower than the polishing rate toward the center 120 of wafer 100 (i.e., edge slow). The difference in polish rates across the wafer may cause the topography of the wafer to be uneven after polishing. For example, the polishing rate profile of FIG. 1 may cause the wafer topography to have low points in the center of the wafer and high points around the edges of the wafer, rather than a flat or planar surface as is desired.
It is desired to have an even polish rate profile across the wafer surface in order to improve the planarity of the polishing process. As illustrated in FIG. 1, an ideal polish rate profile is illustrated in FIG. 1 by dashed line 150. In order to arrive at the ideal polish rate profile 150, what is needed is method to increase the polish rate at the edges of the wafer 110, and decrease the polish rate at the center of the wafer 120. The ideal polish rate profile 150 will improve the surface planarity of the polishing process.
FIGS. 2 and 3 also illustrate examples wherein the polishing rates are uneven/unstable across the surface of a wafer. FIG. 2, illustrates the opposite effect of FIG. 1, wherein the polishing rate at the edges 210 of wafer 200 is faster than the polishing rate toward the center 220 of wafer 200 (i.e., center slow). Thus in FIG. 2, what is needed is a method to decrease the polish rate at the edges of the wafer 210, and increase the polish rate at the center of the wafer 220, in order to obtain the ideal polish rate profile 250. FIG. 3, illustrates a worst case scenario wherein the polishing rate varies randomly across the entire wafer surface. Thus in FIG. 3, what is needed is a method to decrease the polish rate in the areas of the wafer 300 where the polish rate is high, and increase the polish rate in the areas of the wafer 300 where the polish rate is low, in order to obtain the ideal polish rate profile 350.
Thus, what is needed is a method to increase the polish rate in the areas of a semiconductor wafer that the polish rate is low and/or decrease the polish rate in the areas of a semiconductor wafer that the polish rate is high in order to improve the planarization process of the semiconductor wafer.